Implementation Of High-k/Metal Gates In High-Volume Manufacturing

October 30, 2017 | Author: Thomas Burke | Category: N/A
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Implementation Of High-k/Metal Gates In High-Volume Manufacturing INTRODUCTION There have been significant breakthroughs in IC technology in the past decade. The upper interconnect layers of the chip transitioned to copper and ultra low k dielectrics to reduce signal delay using a new dual damascene integration approach. Advanced patterning films have enabled the introduction of double patterning schemes and dual exposure lithography allowing circuit patterns to be printed at the sub-45nm node. Further, introduction of uniaxial stress at the 90nm logic node using a combination of strain engineering films boosted logic cell performance to meet 45nm node logic requirements. Reliable gate oxynitride material of only a few atomic monolayers in thickness is now routinely used in high performance devices, enabling smaller, faster transistors. Despite all these remarkable advancements, Intel co-founder Gordon Moore stated that the introduction of new high-k and metal materials to the gate is the biggest change in transistor technology in nearly 40 years. Needed to keep Moore’s Law on track, high-k and metal gate implementation has been one of the industry’s grand challenges. This white paper reviews the history of the transition from SiO₂ and polysilicon gates to high-k/metal gates (Figure 1). Areas discussed include material selection, best integration methods and tool sets most suited for high-volume high-k/metal gate manufacturing starting at the 45nm logic technology node and for memory cells.

Figure 1: High-k/metal gate transistors provide significant increase in switching speed and leakage reduction, ensuring continuation of Moore’s Law.

WHY HIGH-K/METAL GATES ARE CRITICAL Smaller transistors require a gate dielectric with increased capacitance. Higher capacitance is achieved by reducing the gate oxide thickness, but this increases gate leakage. Below 5.0nm in thickness, the leakage is unacceptably high when SiO₂ is used as the gate dielectric material. As a result, integrated device manufacturers introduced nitrided oxides SiON as a gate dielectric. Nitrided oxides were initially processed thermally by annealing in N₂O, NH₃ or NO chemistry. Plasma oxynitrides were later introduced as the dielectric thickness was scaled below 3.0nm to incorporate higher levels of nitrogen. However, leakage in this ultra thin gate dielectric continued

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to be a problem and further oxide scaling was not an option. The 90nm logic node saw the final scaling of gate oxynitrides at 1.2nm; it could not be scaled beyond this point. The 65nm logic node continued with this gate dielectric thickness and minor gate CD scaling but emphasized integrated more strain-inducing layers into the process flow. The solution was to replace the oxynitride with a higher dielectric constant (k) to allow a higher capacitance with no electrical thickness penalty and reduced gate leakage. Figure 2 shows the gate leakage as a function of thickness for oxides, oxynitrides, and high-k dielectrics. For a given gate dielectric thickness, the hafnium-based (Hf) high-k dielectric coupled with a metal gate reduces the gate leakage by several orders of magnitude. This permits the poly critical dimensions of the transistor to be scaled, allowing Moore’s Law to continue. In the early stages of high-k dielectric development, a material incompatibility between the polysilicon gate electrode and high-k dielectric was discovered. At issue were the high defect rates at the interface of high-k and polysilicon and the lower electrical mobility of the devices. The early solution to this problem was to replace the polysilicon with a metal electrode. High mobility devices with high-k gate dielectric and TiN electrode were processed and reported to have successfully circumvented mobility issues. Since CMOS processing requires both NMOS and PMOS devices, high-k/metal gate implementation now requires three new materials: a material with high dielectric constant for the dielectric layer and a metal (replacing poly) for NMOS and a metal for PMOS, with both metals having “work function”. An alternative method of implementing high-k/metal gates eliminates the need for two different metals by depositing two different dielectrics. This method mixes a Hf high-k dielectric with another dielectric containing more electropositive atoms such as lanthanum oxide in the case of NMOS devices. In the case of the PMOS devices, the Hf-based dielectric must be paired with a dielectric containing more electronegative atoms such as an aluminum-based oxide.

Figure 2: High-k enables scaling to 100x reduction in gate leakage. The Equivalent Oxide Thickness (EOT) of a dielectric is inversely proportional to its dielectric constant.

The two approaches, however, require distinctly different materials, integration methods and even tool sets in highvolume manufacturing.

THE NEW HIGH-K GATE DIELECTRICS After more than ten years of research, Hf-based dielectrics have become the material of choice to replace SiO₂. Hf-based dielectrics include hafnium-oxide (HfO₂, k~25) which is most suitable for high-performance ICs such as microprocessors. Hafnium-silicate, and hafnium-siliconoxynitride (HfSiO/HfSiON, k~15) are suitable for low power-consumption chips. One of the most significant challenges encountered when introducing high-k materials was maintaining the transistor’s high drive current. To eliminate this mobility degradation, a thin oxynitride interface layer must be maintained between the silicon and high-k (Figure 3). This extends the oxynitride-silicon interface that has provided excellent carrier mobility, interface stability and device reliability for the last three or four technology nodes.

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metals must withstand the high thermal requirements of the current CMOS integration flows where high temperatures are used. Most metals with high work function have stable bulk characteristics after high thermal processing but alter their interface characteristics with the high-k dielectric after high temperature processing.

Figure 3: An integrated SiON and HfO₂ stack with metal gate indicates an atomically smooth interface where the intermixing of Hf with the oxynitride provides a net higher k for the entire stack.

THE NEW METAL GATES Replacing the polysilicon gate materials with metal eliminates incompatibility between the high-k dielectric and poly electrode. Significant research was invested on finding metal electrodes with the correct work function. Such

Since conventional CMOS processing is incompatible with metal gate electrodes, a new low thermal budget CMOS flow was needed. Such a process could be a gate-last or damascene flow (Figure 4). In this flow, the metal gate material is deposited inside poly trenches after the high temperature steps of thermal processing and dopant activation. In a gate-first flow, however, the threshold voltage needs to be adjusted by alternative methods such as creation of a dipole field inside the dielectric that adjusts the threshold voltage independent of the work function of the metal. The tool set required for metal deposition is a combination of physical vapor deposition (PVD) and atomic layer deposition (ALD).

Figure 4: Gate-last integration is a low temperature metal gate process. The high-k film is deposited prior to poly and undergoes standard prcess flow. After PMD deposition and CMP, the poly from both NMOS and PMOS are removed simultaneously. After metal gate depostion, one lithography step is required to remove the first metal deposited. Complete metal fill and a metal CMP is required.

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Significant advances have been made in ALD, PVD metal and dielectric deposition technologies and these tools are ready for high-volume manufacturing of high-k/metal gate.

of defects are essential methodologies to shorten the yield learning curve during the development phase, as well as for finding the root causes of excursions during production.

ETCH, CMP AND METROLOGY

TWO INTEGRATION APPROACHES

The implementation of high-k/metal gates introduces new etch, chemical mechanical polish (CMP) and metrology challenges. In the gate-first scheme, both the dielectric cap layer and metal gate deposition have to be low-damage processes with excellent uniformity. High-k materials present profile, selectivity, and residue control challenges for etch that demand a wider process window to overcome. To ensure the ultimate electrical viability of the device, the high-k etch must achieve vertical and smooth profiles all the way to the silicon interface and avoid any recess into the silicon in the S/D areas beneath the gate.

Several integration schemes are being considered with the two main approaches being “gate-last” and “gate-first.” The gate-last approach (Figure 4) is considered a low-temperature process since the metal is not exposed to high temperatures. The dielectric itself, however, is deposited prior to gate processing in traditional fashion. A major advantage of this approach is that metals with known work functions can be integrated with a relatively simple process flow without exposure to a high thermal budget.

Avoiding silicon recess calls for a chemical etch action, which does not pose the risks inherent in physical bombardment by reactive ion etch. However, at conventional processing temperatures, etching cannot clear a full vertical profile all the way to the silicon interface. Instead, it tends to leave behind a foot-shaped film of the high-k material at the interface, generating undesirable residues. Hightemperature etch processing, on the other hand, energizes the chemical etch action to eliminate the foot with infinite selectivity to the underlying silicon while enhancing the volatility of high-k etch byproducts to produce residuefree surfaces.

In the gate-first integration flow, as shown in Figure 5, with the exception of inserting the new high-k/metal gate materials, a standard transistor process is used.

For the gate-last flow, new polishing techniques need to be developed to remove the low resistivity metals used to fill the poly trenches. Such a process must maintain uniformity with no dishing of the electrodes as this could lead to subsequent contact lithography and processing issues. Detection of small defects between dense structures requires a coherent, high intensity illumination source, such as a short-wavelength laser, to penetrate between the structures without losing inspection sensitivity. With the introduction of new materials in high-k/metal gate processes, defect composition analysis and cross sectioning

Figure 5: Gate-first integration inserts the high-k metal steps into the standard process flow. The dielectric cap layers are deposted after the blanket high-k depostion on the oxynitride. One lithography step is required to remove the first cap layer. A single metal is deposited on both the cap layers, which tune the device Vth.

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HIGH-K/METAL GATE IN CMOS MEMORY

SUMMARY

Novel materials and designs are being considered for CMOS memory devices such as 3D SONOS arrays, Resistive RAM (including chalcogenides), Ferroelectric RAM, Magnetic RAM, nanocrystalline and high-k/metal gate charge trap flash. Among this list, leading memory IDMs have been investigating the use of high-k/metal gates with charge trap flash devices, such as the TANOS (TaN-Al₂O₃-SiN-Oxide-Si) cell structure as illustrated in Figure 6.

Starting at the 45nm node, integrated device manufacturers of both logic and CMOS memory will implement high-k/ metal gates in high-volume manufacturing. Flash memory will take advantage of high metal work functions and band gap engineered charge trap memories by implementing high-k and metal gate. Two metals and one dielectric (gate last) versus two dielectrics and one metal (gate first) are two approaches taken by lead logic device manufactures for material choices. Each choice, however, requires a unique integration scheme and unique tool sets. Both the equipment industry and the lead device manufactures are now ready to put this long awaited change in high-volume manufacturing.

Challenges with high-k/metal gate implementation in the Flash memory process flow are similar to the logic gate-first process in terms of material stability and variability with high temperature processing. However, only a single metal with a high work function and high-k dielectric are utilized for all cells.

CONTACTS Technology: [email protected] [email protected] [email protected] Media:

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Figure 6: An example of a high-k metal gate in CMOS memory is the TANOS structure. TANOS cell patterning courtesy of Maydan Technology Center, Applied Materials.

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